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An All Digital Phase-Locked Loop System with High Performance on Wideband Frequency Tracking

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成果类型:
期刊论文、会议论文
作者:
Shan Chang-hong*;Chen Zhong-ze;Jiang Jin-xiong
通讯作者:
Shan Chang-hong
作者机构:
[Chen Zhong-ze; Shan Chang-hong; Jiang Jin-xiong] Univ S China, Coll Elect & Elect Engn, Hengyang 421001, Hunan, Peoples R China.
通讯机构:
[Shan Chang-hong] U
Univ S China, Coll Elect & Elect Engn, Hengyang 421001, Hunan, Peoples R China.
语种:
英文
关键词:
All Digital Phase-Locked Loop (all DPLL);Wideband Frequency Tracking;Filter;VHDL;FPGA
期刊:
HIS 2009: 2009 NINTH INTERNATIONAL CONFERENCE ON HYBRID INTELLIGENT SYSTEMS, VOL 3, PROCEEDINGS
年:
2009
卷:
3
页码:
460-463
会议名称:
2009 Ninth International Conference on Hybrid Intelligent Systems(第九届混合智能系统国际会议 HIS 2009)
会议论文集名称:
2009 Ninth International Conference on Hybrid Intelligent Systems(第九届混合智能系统国际会议 HIS 2009)论文集
会议时间:
2009-08-12
会议地点:
沈阳
会议赞助商:
沈阳师范大学
机构署名:
本校为第一且通讯机构
院系归属:
电气工程学院
摘要:
Based on synthesizing most sorts of phase/frequency locking mechanisims respectively shown in different conventional all digital phase-locked loop (all DPLL) systems, a novel all DPLL, which is with higher performances on wideband frequency tracking and also possesses a balance mechanisim for improving system performance on noise reduction as well as shortening time for arriving at a synchronous state, is proposed. The system has a parameters adaptation enginery, which ensures the synchronization of the phase/frequency of the output signal with that of input when a wide range of variance in ph...

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